1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of testing of integrated circuits to determine reliability of the circuits.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS and as well as metal insulator semiconductor (MIS) technologies are currently among the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors are formed on a substrate including a crystalline semiconductor layer. Generally, MOS technology involves forming a poly/metal gate, as well as dielectric and semiconductor substrates.
Various processes are performed on semiconductor substrates in manufacturing integrated circuit products. When integrated circuits are formed, tests are performed to determine the correctness in the operation of the circuits. Manufacturers generally perform various tests to determine the effects of the various processes on the performance and reliability of the circuits. Various quality or performance criterions may be used in determining whether the integrated circuits meet quality standards.
Dielectric weakening and/or failure with respect to time, temperature, and/or voltage are major concerns with regard to reliability failure of circuits manufactured using current semiconductor technology. In some instances, defects during processing can lead to dielectric failure (e.g., time dependent dielectric breakdown (TDDB) failure mechanism), which may result in a decrease in the overall reliability of the semiconductor devices. Process problems may affect the characteristics of the transistors and/or may cause weakening or failure of dielectric, which may lead to problems such as loss of integrity of the gate of a transistor. Therefore, tests to check various failure mechanisms (e.g., TDDB) are performed for testing the reliability of the integrated circuits.
Manufacturers generally perform tests that help determine the dielectric failure prospects in order to determine the reliability of the circuits. Generally, a primary test that is performed in order to determine the dielectric failure prospects is the TBBD test.
The TDDB test relates to determining when a circuit portion, such as the gate of a MOSFET device, breaks down. This may be caused by weakness in portions of the dielectric. A determination may be made as to when the dielectric part of the circuit portion breaks down at certain particular current-levels, voltage levels, and/or temperature levels. In the example of a MOSFET, the breakdown would keep the gate of the MOSFET from operating properly as a switch that could control the current flow through the source and the drain of the MOSFET.
Accurate lifetime prediction for TDDB requires a large set of samples to be tested under accelerated voltage/temperature stress conditions. One of the problems with the state-of-the-art testing systems is that the number of devices under test (DUTs) at a given time period is limited. For example, the number of DUTs are limited by the number of test pins available on a testing circuit. This causes several problems, such as limitations as to the data available for determining breakdown statistics for a particular accelerated test, delays introduced in testing a large number of devices sequentially, which can change the physics of trapping and de-trapping of charge carriers with respect to breakdown. Moreover, state-of-the-art testing regimen involves determining a so-called beta parameter. When using testing across the wafer to determine beta, the state-of-the-art beta parameter provides indications of global variability, but fail to efficiently capture the local variability at the chip level. Thus, the intrinsic reliability is not efficiently provided by the state-of-the-art testing regimen. This makes the more difficult the task of determining whether one process produced intrinsically superior dielectric from another.
The present disclosure may address and/or at least reduce one or more of the problems identified above.